\CMOS\ compatible on-chip decoupling capacitor based on vertically aligned carbon nanofibers
By A.M. Saleem and G. G
Published in Solid-State Electronics
NULL
2015
Abstract
On-chip decoupling capacitor of specific capacitance 55 pF/?m2 (footprint area) which is 10 times higher than the commercially available discrete and on-chip (65 nm technology node) decoupling capacitors is presented. The electrodes of the capacitor are based on vertically aligned carbon nanofibers (CNFs) capable of being integrated directly on \CMOS\ chips. The carbon nanofibers employed in this study were grown on \CMOS\ chips using direct current plasma enhanced chemical vapor deposition (DC-PECVD) technique at \CMOS\ compatible temperature. The carbon nanofibers were grown at temperature from 390
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